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// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
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// agreement for further details.

`timescale 100 ps / 1 ps

`include "logic.svh"

module i3c_phy import i3c_pkg::*; (
    // Clock & reset interface
    input  wire          clk,
    input  wire          reset_n,

    // Configuration signals
    `LOGIC_MODPORT(i3c_phy_cfg_if, slave) cfg,

    // MGMT signals
    `LOGIC_MODPORT(i3c_phy_mgmt_if, slave) mgmt,

    // I3C bus
    input  wire          scl_data_in,
    output wire          scl_data_out,
    output wire          scl_oe,

    input  wire          sda_data_in,
    output wire          sda_data_out,
    output wire          sda_oe,

    // External Pull-up Resistor enable
    output wire          pur_oe
);

    link_state_t         link_state;
    link_mode_t          link_mode;
    transition_status_t  transition_status;
    logic                transition_status_valid;
    logic                gen_data;
    logic                cap_data;
    logic                cap_data_valid;
    transition_t         transition_request;
    logic                ack_nack_status;
    logic                ack_nack_status_valid;
    logic                stage_last;
    logic                ibi_detected;
    logic                i3c_reset_n;

    i3c_phy_link_mgmt i3c_phy_link_mgmt_inst (
        // clock interface
        .clk                        (clk),
        .reset_n                    (reset_n),

        .scl_data_in                (scl_data_in),
        .scl_data_out               (scl_data_out),
        .scl_oe                     (scl_oe),

        .sda_data_in                (sda_data_in),
        .sda_data_out               (sda_data_out),
        .sda_oe                     (sda_oe),

        .operation_mode             (cfg.operation_mode),
        .device                     (cfg.device),
        .mode                       (cfg.mode),
        .link_state                 (link_state),
        .link_mode                  (link_mode),

        .request                    (mgmt.request),
        .busy                       (mgmt.busy),

        .gen_data                   (gen_data),
        .cap_data                   (cap_data),
        .cap_data_valid             (cap_data_valid),

        .transition_request         (transition_request),
        .transition_status          (transition_status),
        .transition_status_valid    (transition_status_valid),

        .ack_nack_status            (ack_nack_status),
        .ack_nack_status_valid      (ack_nack_status_valid),
        
        .stage_last                 (stage_last),
        .ibi_detected               (ibi_detected),
        .pur_oe                     (pur_oe)
    );

    i3c_phy_cmd i3c_phy_cmd_inst (
        // clock interface
        .clk                        (clk),
        .reset_n                    (reset_n),

        .error                      (),

        // MGMT signals
        .busy                       (mgmt.busy),
        .status                     (mgmt.status),
        .request                    (mgmt.request),
        .wr_data                    (mgmt.wr_data),
        .rd_data                    (mgmt.rd_data),
        .rd_data_valid              (mgmt.rd_data_valid),

        // Link MGMT signals
        .link_state                 (link_state),
        .link_mode                  (link_mode),
        .gen_data                   (gen_data),
        .cap_data                   (cap_data),
        .cap_data_valid             (cap_data_valid),
        .device                     (cfg.device),

        .transition_request         (transition_request),
        .transition_status          (transition_status),
        .transition_status_valid    (transition_status_valid),

        .ack_nack_status            (ack_nack_status),
        .ack_nack_status_valid      (ack_nack_status_valid),

        .stage_last                 (stage_last),
        .ibi_detected               (ibi_detected)
    );

endmodule